The present invention relates to a method for fabricating a nonvolatile semiconductor memory device.
In recent years, nonvolatile semiconductor memory devices have been widely used as: storage media, to/from which data can be written and read out at a high speed, for portable electronic information processing units and memory cards; alternatives to magnetic storage media; or parts of high-performance LSI's. Thus, the nonvolatile semiconductor memory devices have significant industrial applicability.
A nonvolatile semiconductor memory device is disclosed, for example, in Japanese Laid-Open Publication No. 7-115142. Hereinafter, the structure of the nonvolatile semiconductor memory device and a method for fabricating the same will be described with reference to FIG. 11 and FIGS. 12A through 12E.
FIG. 11 is a cross-sectional view showing the structure of the nonvolatile semiconductor memory device described in the above-identified Japanese Laid-Open Publication No. 7-115142. As shown in FIG. 11, a step portion 102 is provided for a semiconductor substrate 101. A tunnel oxide film 104, a floating gate electrode 105, a capacitive insulating film 106 and a control gate electrode 107 are deposited in this order so as to overlap the upper- and lower-level surfaces of the step portion 102. In the regions located on right- and left-hand sides of the floating gate electrode 105 in the semiconductor substrate 101, highly doped source/drain regions 108 and 109 are respectively formed.
By providing the step portion 102 for the semiconductor substrate 101 and forming the floating gate electrode 105 to overlap the upper- and lower-level surfaces of the step portion 102, part of the floating gate electrode 105 exists in front of the direction in which channel hot electrons move, i.e., the average direction in which the velocity vectors are directed (the direction from left to right in FIG. 11) during the write operation for injecting electrons into the floating gate electrode 105. As a result, since the hot electrons can be injected into the floating gate electrode 105 more efficiently, the write efficiency is improved.
FIGS. 12A through 12E are cross-sectional views illustrating a method for fabricating the nonvolatile semiconductor memory device described in the above-identified Japanese Laid-Open Publication No. 7-115142.
First, in the process step shown in FIG. 12A, an element isolation region (not shown) is formed of a LOCOS film on the surface of a semiconductor substrate 101 made of P-type silicon. Then, an oxide film used as a mask for forming a step is formed over the entire surface of the substrate 101 and patterned, thereby forming an oxide film mask 111. And the substrate 101 is etched by using the oxide film mask 111 as a mask, thereby forming a step portion 102 in the semiconductor substrate 101.
Next, in the process step shown in FIG. 12B, arsenic ions are implanted by using the oxide film mask 111 as a mask and in accordance with large-angle-tilt ion implantation under the conditions where the implant angle is set at 30 degrees, the implant energy is set at 20 KeV and the dose is set at 1.0.times.10.sup.15 cm.sup.-2, thereby forming a lightly doped drain 103 in the semiconductor substrate 101 so as to cover the side and lower-level surfaces of the step portion 102. After the fabrication process is completed, the thickness of the lightly doped drain 103 reaches about 0.05 .mu.m because of thermal diffusion of the implanted impurity.
Subsequently, in the process step shown in FIG. 12C, the oxide film mask 111 is removed and the semiconductor substrate 101 is thermally oxidized, thereby forming a silicon oxide film 104x having a thickness of about 10 nm on the surface of the semiconductor substrate 101. Then, CVD and thermal oxidation processes are further performed, thereby forming a CVD polysilicon film 105x having a thickness of about 200 nm, an ONO film 106x having a thickness of about 20 nm and a CVD polysilicon film 107x having a thickness of about 200 nm in this order on the silicon oxide film 104x.
Thereafter, in the process step shown in FIG. 12D, the respective films 104x, 105x, 106x and 107x are patterned, thereby forming a tunnel oxide film 104, a floating gate electrode 105, a capacitive insulating film 106 and a control gate electrode 107 (each having a stepped shape) so as to overlap the upper- and lower-level surfaces of the step portion 102.
Then, in the process step shown in FIG. 12E, arsenic ions are implanted by using the control gate electrode 107 and the underlying layers as a mask under the conditions where the implant energy is set at 50 KeV and the dose is set at 3.0.times.10.sup.15 cm.sup.-2, thereby forming a highly doped source/drain regions 108 and 109 in the respective regions of the semiconductor substrate 101 on right- and left-hand sides of the floating gate electrode 105. In this manner, a memory cell for the nonvolatile semiconductor memory device is formed.
In the subsequent process steps (not shown), an interlevel insulating film, contact holes, interconnections and the like are formed by performing known process steps.
In the process step shown in FIG. 12B for forming the lightly doped drain 103, the location of the drain 103 is determined by the oxide film mask 111 used when the step portion 102 is formed. On the other hand, in the process step shown in FIG. 12E for forming the source 108, the location of the source 108 is determined by the accuracy during the implantation of impurity ions using the floating gate electrode 105, the control gate electrode 107 and the other layers as a mask. Thus, depending upon the positional misalignment between a resist mask for forming the oxide film mask 111 and a resist mask for forming the floating gate electrode 105 and the other layers, the effective channel length of a resulting memory cell transistor adversely varies. Accordingly, in view of the fact that the positioning accuracy of a resist mask is about 0.1 .mu.m according to the current photolithography technique, it is difficult to satisfactorily maintain the operating characteristics of a nonvolatile semiconductor memory device having an effective channel length, which is about to be reduced to about 0.3 .mu.m.
The object of the present invention is to provide a nonvolatile semiconductor memory device having hot electron injection efficiency improved by providing a stepped floating gate electrode on the surface of a semiconductor substrate with a structure in which the effective channel length of a memory cell transistor does not depend on the positional misalignment between the masks used in a photolithography process for forming the gate electrode.